EQUA35E5D1H-24.5535M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Sep 22, 2020)
191 SVHC
ITEM DESCRIPTION
Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVCMOS (CMOS) 3.0Vdc 6 Pad
2.5mm x 3.2mm Ceramic Surface Mount (SMD) 24.5535MHz -30°C to +60°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Stability
Frequency Stability vs. Frequency
Tolerance
Frequency Stability vs. Input Voltage
Frequency Stability vs. Load
Frequency Stability vs. Reflow
Frequency Stability vs. Aging
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Control Voltage
Frequency Deviation
Linearity
Transfer Function
Modulation Bandwidth
Input Impedance
Phase Noise
24.5535MHz
±5.0ppm Maximum (Inclusive of Operating Temperature Range, at Vdd=3.0Vdc, at Vc=1.5Vdc)
±1.0ppm Maximum (at 25°C ±2°C, at Vdd=3.0Vdc, at Vc=1.5Vdc ±0.1Vdc, Pre-Reflow)
±0.2ppm Maximum (±5%)
±0.2ppm Maximum (±2pF)
±1.0ppm Maximum (at 25°C, 24 hours after reflow, 1 time)
±1ppm/Year Maximum (at 25°C)
-30°C to +60°C
3.0Vdc ±5%
20mA Maximum (Unloaded)
90% of Vdd Minimum (IOH = -4mA)
10% of Vdd Maximum (IOL = +4mA)
3nSec Maximum (Measured at 10% to 90% of Waveform)
50 ±5(%) (Measured at 50% of Waveform)
15pF Maximum
CMOS
1.5Vdc ±1.0Vdc
±8ppm Minimum
10% Maximum
Positive Transfer Characteristic
10kHz Minimum (Measured at -3dB)
1MOhms Minimum
-64dBc/Hz at 10Hz offset; -96dBc/Hz at 100Hz offset; -124dBc/Hz at 1kHz offset; -131dBc/Hz at 10kHz offset; -
132dBc/Hz at 100kHz offset; -149dBc/Hz at 1MHz offset; -157dBc/Hz at 10MHz offset; -159dBc/Hz at 20MHz offset (All
Values are Typical)
Output Enable (OE)
90% of Vdd Minimum or No Connect to Enable Output
10% of Vdd Maximum to Disable Output (High Impedance)
100nSec Maximum
50nSec Maximum
15mA Maximum (Without Load (Pin 2 = Ground))
1.5pSec Maximum (Fj=12kHz to 20MHz (Random))
0.2pSec Typical
2pSec Typical
3pSec Maximum
30pSec Maximum
Output Control Function
Output Control Input Voltage Logic
High (Vih)
Output Control Input Voltage Logic
Low (Vil)
Output Enable Time
Output Disable Time
Output Enable Current
RMS Phase Jitter
Period Jitter (Deterministic)
Period Jitter (Random)
Period Jitter (RMS)
Period Jitter (pk-pk)
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 1 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQUA35E5D1H-24.5535M
ELECTRICAL SPECIFICATIONS CONTINUED
Start Up Time
Storage Temperature Range
10mSec Maximum
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 2 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQUA35E5D1H-24.5535M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
CONNECTION
Control Voltage
Output Enable (OE)
Case/Ground
Output
Do Not Connect
Supply Voltage
0.80 ±0.10 (X4)
2.50
±0.10
1.70
MAX
1.285
±0.10
3
3.20
±0.10
2.57
±0.10
2
1
0.90 ±0.10
1.55
±0.10
4
0.50
±0.10 (X2)
MARKING
ORIENTATION
1
2
3
4
5
6
0.475
±0.10 (X2)
5
6
0.55
±0.10 (X4)
LINE MARKING
1
2
E24.553
E=Ecliptek Designator
XXXXX
XXXXX=Ecliptek
Manufacturing Identifier
Terminal Plating Thickness:
Gold (0.3 to 1.0µm) over Nickel (1.27 to 8.89µm).
Suggested Solder Pad Layout
All Dimensions in Millimeters
2.50
±0.10
1.10 (X4)
1.70
MAX
0.90
±0.10
3
2.57
±0.10
0.70 (X2)
0.75 (X6)
4
5
6
0.55
±0.10 (X4)
0.50
±0.10 (X2)
0.80
±0.10
(X4)
3.20
±0.10
MARKING
0.60 (X4)
ORIENTATION
2
1
0.50 (X2)
Solder Land
(X6)
1.285 ±0.10
1.55
±0.10
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 3 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQUA35E5D1H-24.5535M
OUTPUT WAVEFORM & TIMING DIAGRAM
V
IH
INPUT
V
IL
CLOCK OUTPUT
V
OH
80% of Waveform
50% of Waveform
20% of Waveform
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 4 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQUA35E5D1H-24.5535M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
Current
Meter
Power
Supply
Voltage
Meter
0.01µF
(Note 1)
0.1µF
(Note 1)
Supply
Voltage Do No
(V
DD
) Connect
Output
Output
Enable
Control
Voltage
Ground
Probe
(Note 2)
C
L
(Note 3)
Power
Supply
Voltage
Meter
Switch
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high
frequency ceramic bypass capacitor close (less than 2mm) to the package
ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance
(>10Mohms), and high bandwidth (>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Power
Supply
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 5 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
